1. Field of the Invention
The present invention relates to a state retention circuit and a method of operation of such a state retention circuit.
2. Description of the Prior Art
Sequential storage circuits that store data in response to a clock signal in data processing circuits are known. These circuits include latch circuits and flip flops and are very important elements of a processing circuit from both a delay and energy standpoint. Flip flops can take the form of master-slave latches which input the data to the master latch during the first phase of the clock cycle and transfer it to the slave latch during the second phase of the clock cycle. This makes them look as though they store data in response to an edge, in other words they appear edge triggered.
An alternative design to these master-slave flip flops is a pulse triggered flip flop which stores data in a single latch in response to a pulse. If the pulse is small and occurs on the edge of the clock it also looks as though the storage element or latch is edge triggered. In effect the latch is transparent when the pulse is high so the storage element can receive the data during the pulse, and is then opaque when the pulse is low so that it is isolated from the input. However, the pulse must be wide enough for the storage element to be able to react during the pulse width and store the data, and not too wide as otherwise the data may “race” through the storage element before it is latched causing potential state errors in downstream circuits.
As process geometries shrink, power consumption is becoming a significant issue. In particular, as threshold voltages reduce, there is an increase in leakage current which gives rise to significant power consumption issues, particularly in battery-powered applications.
Power-gating is one of the most effective methods to reduce chip power. In accordance with such techniques, inactive blocks are shut down by turning off power supplies to those blocks through switch cells. Whilst critical state of the design can be shifted out and saved in memory before the power is removed from such blocks, and then retrieved from the memory at block wakeup time, this state saving and restoring process can give rise to significant performance degradation.
Accordingly, in order to enable rapid resumption of operations from a power-gated mode, many power-gating designs implement state retention storage structures which are able to retain state during a low power mode, so that at wakeup time the retained state is quickly available to allow resumption of operation. The earlier mentioned master slave flip-flops and/or pulse triggered flip-flops can be configured to provide such state retention storage circuits.
Often flip-flops which possess a retention mode require the input clock to be stopped in a specific state prior to the retention mode being entered, and to be in the same specific state when the retention mode is exited. If these conditions are not met, the flip-flop can fail to maintain the same state during the retention mode and subsequent exit from the retention mode. Such flip-flops are often referred to as clock dependent retention flip-flops, and designs for such clock dependent retention flip-flops are quite common. However, such clock dependent retention flip-flops place significant constraints upon the design through their requirement for the clock signal to be in a specific state on both entry to, and exit from, the retention mode.
Accordingly, it would be desirable to provide a retention storage structure where the input clock could be in any of the valid clock states when the retention mode is entered and be in any of the valid clock states when the retention mode is exited, whilst still ensuring that the state retained in the storage structure is not corrupted during the retention mode. Flip-flops which provide such functionality are referred to as clock independent retention flip-flops. In particular, such clock independent retention flip-flops are able to output, on exit from the retention mode, the same state that was stored just prior to entry of the retention mode, for all of the four possible combinations of entry and exit clock states indicated below:
CLOCK STATE WHEN ENTERINGCLOCK STATE WHEN EXITINGRETENTION MODERETENTION MODE00011011
The state retained in a clock independent retention flip-flop should also remain uncorrupted irrespective of transitions in the clock that occur during the retention mode.
When the flip-flop is in retention mode, the power to various circuits, including for example the portions of the flip-flop which do not store the state, may be removed. When the power is removed this is referred to as a power down state (also referred to herein as a low power mode of operation). Both clock dependent and clock independent retention flip-flops must not modify the internal state of the flip-flop throughout the power down and retention sequence, and must not modify the state of the flip-flop during the transition from retention mode to non-retention (normal) mode. It has proved difficult to achieve these characteristics for clock independent retention flip-flops with designs that are simple enough to implement in a typical layout. Often, the earlier mentioned master-slave latch form of flip-flops have been used as the basis for implementations, and laying out such designs is often impossible in small cell heights.
The article “Area and Power-Delay Efficient State Retention Pulse-Triggered Flip-Flops with Scan and Reset Capabilities” by K Shi, Pages 170 to 175, IEEE International Conference on Computer Design, 2008, 12 to 15 Oct. 2008, discusses various designs of area and power-delay efficient state retention pulsed flops. FIG. 2 of that document illustrates a clock independent retention flip-flop based on a pulse triggered flip-flop. In accordance with the discussed design, additional isolation devices are added to the data path to block the ability of the generated pulses to vary the data in the storage element during retention mode. However, such an approach adversely affects performance, due to the insertion of additional devices along the data path, and also exhibits power consumption problems due to the continued operation of the pulse generator, the driving of the additional isolation devices, etc.
It would accordingly be desirable to provide an improved design of clock independent retention storage structure.